Ferroelectric memory devices use ferroelectric material for a memory cell capacitor to provide nonvolatile memory devices. A ferroelectric capacitor has hysteresis properties, so that a remanent polarization of different polarity according to the electric field history remains even if the electric field is zero. Therefore, a nonvolatile memory device can be implemented by representing stored data by the remanent polarization of the ferroelectric capacitor. It is known to use KNO.sub.3, PbLa.sub.2 O.sub.3 --ZrO.sub.2 --TiO.sub.2, and PbTiO.sub.3 --PbZrO.sub.3, and other materials as the ferroelectric material that forms the capacitor.
In U.S. Pat. No. 4,873,664, two types of ferroelectric memory devices are disclosed. In a first type, a memory cell comprises one transistor and one capacitor per bit (hereinafter, referred to as "1T/1C"). One dummy memory cell (also referred to as a reference cell) is provided for, for example, 256 main memory cells (also referred to as normal cells). In a second type, a memory cell comprises two transistors and two capacitors per bit (hereinafter, referred to as "2T/2C"), and a dummy memory cell is not provided therein. Complementary data is stored in a pair of ferroelectric capacitors.
According to the above-mentioned 1T/1C type ferroelectric memory device, a reference memory cell capacitor may have, for example, twice the capacitance (that is, twice the area) of a main memory cell capacitor. Also, the size of the reference memory cell capacitor is different from that of the main memory cell capacitor. Thus, the size may be determined according to the performance of the ferroelectric capacitor.
In a conventional 1T/1C type ferroelectric memory device, the size of a reference memory cell capacitor may be set differently from that of a main memory cell capacitor. However, the operational margin may be reduced, particularly at low voltage, due to the performance variation and voltage dependency of the ferroelectric capacitor. In the 2T/2C type ferroelectric memory device, operation may be stable at low voltage, but the memory cell area for one bit may be almost twice that of the 1T/1C type.
In addition, in conventional 2T/2C type or 1T/1C type devices, it may be difficult to perform a margin test of the performance of a ferroelectric capacitor. Thus, it may be difficult to remove a ferroelectric capacitor having low performance. It would be desirable to provide circuits and methods for testing the performance margin of a ferroelectric capacitor.